There are many instances on advanced ICs where voltage level translator circuits are needed to interface between circuit blocks with different power supplies, such as on DRAMs, EPROMS, EEPROMs, etc., where control signals with a normal swing (i.e. 5 V) between V.sub.CC and V.sub.SS need to interface with row decoders which have a much higher voltage swing of V.sub.CC ' (where V.sub.CC ' is &gt;V.sub.CC) and V.sub.SS during cell programming.
Also, in order to maintain device reliability for future IC generations with sub-micron devices having a feature size smaller than 0.6 .mu., these devices will be required to operate under a supply voltage of &lt;4 V. Yet, voltage level translators may still be required to interface with circuit blocks having a supply voltage of &gt;4 V that is generated either internally or externally, for device performance enhancement.
Thus, it will become very important to have a voltage level translator with minimum propagation delay for maximum speed, as well as one with minimal power dissipation, in order to promote long term operating reliability while providing optimum circuit performance.
In FIG. 1a, a CMOS Voltage Converter described in U.S. Pat. No. 4,958,091, by Gregory N. Roberts, is shown. In addition, FIGS. 1b and 1c diagram a computer simulation of the circuit action of FIG. 1a in comparison with computer simulations of the present invention which is shown in FIG. 3a. The output of the present invention (FIG. 3a) is labeled OUT1 and the output of FIG. 1a is labeled OUT2.
As can be seen from the circuit simulation of FIG. 1b, for an input with a high to a low transition, the propagation delay for both circuits is essentially the same. However, during a low to high transition, shown in FIG. 1c, the circuit of the present invention is considerably faster. The speed of the present invention is attributed to node C being able to rise fully to V.sub.CCR, thus allowing Q.sub.11 to fully turn on while partially turning off Q.sub.9, which allows the present invention to discharge the output faster. The lack of discharge speed in FIG. 1a, is due to series transmission gate, Q5, between nodes E and F that allow node F to only rise to V.sub.CCR.sup.-V.sub.t initially, thus causing a weaker turn on of Q.sub.11. Due to the weak turn on of Q.sub.11 and Q.sub.9 always being fully on instead of partially off, as well as a weaker turn off of Q.sub.8, the output is discharged at a slower rate which also causes a considerably higher crossing current at the output stage, as compared to a lower crossing current of the present invention.
A high-voltage translator circuit disclosed in an article submitted by McConnell et. al., entitled "An Experimental 4-Mb Flash EEPROM with Sector Erase," IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 4, pp. 484-491, APRIL 1991, has been reproduced in FIG. 2a in order to show computer simulation comparisons between this circuit and the present invention.
As can be seen from the circuit simulation of FIG. 2b, the power dissipated for the circuit of FIG. 2a, represented by curve VCCP2, is substantially higher than the power dissipated by that of the present invention, represented by curve VCCP1, during a high to low transition. This difference in power dissipation is due to the intercoupling employed in the present invention versus that of FIG. 2a. By connecting the gate of Q.sub.6 to the input of the inverter stage and the gate of Q.sub.9 to node C in the present invention, versus having these gates grounded, as in FIG. 2a, the crossing current is reduced, thereby reducing the power dissipated by the present invention as compared to the power dissipated by the circuit of FIG. 2a. The low crossing current of the present invention is due to the partial turning off of p-channel transistors Q.sub.6 and Q.sub.9 versus being always fully on during transition, as in the circuit of FIG. 2a.